always block in Verilog HDL is behavioural modeling and using this, we can describe combinational circuit, flip-flops, sequential circuits, and finite state machine. Using always block, we can write code in higher level like writing an algorithm and it is much easier to write Verilog code in always block.
1. If there is multi-line statement in always block, use begin and end statement and wire code inside begin and end
2. assigning inside always block must be reg type
always @ (senstivity list) is the syntax for using always block.
module gate(a,b,s,y); input a,b,s; output reg y; always @ (*)begin if(s) y = a; else y = b; end endmodule
module gate(clk,reset,d,q); input clk,reset,d; output reg q; always @ (posedge clk)begin if(reset) q <= 0; else q <= d; end endmodule
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