Always block in Verilog

always block in Verilog HDL is behavioural modeling and using this, we can describe combinational circuit, flip-flops, sequential circuits, and finite state machine. Using always block, we can write code in higher level like writing an algorithm and it is much easier to write Verilog code in always block.

Few rules for always block

1. If there is multi-line statement in always block, use begin and end statement and wire code inside begin and end

2. assigning inside always block must be reg type

always @ (senstivity list)

always @ (senstivity list) is the syntax for using always block.

If you are describing a combinational circuit, use * in sensitivity list
If you are clocked circuit, use posedge clk for positive edge trigger and negedge clk (inside sensitivity list) for negative edge triggered circuit
if you are using asynchrounous reset, use posedge clk or negedge reset inside senstivity lise

always block examples

Combinational circuit - 2X1 MUX

module gate(a,b,s,y);
input a,b,s;
output reg y;

always @ (*)begin
if(s)
    y = a;
else
    y = b;
end
                
endmodule

Sequential circuit - D flip-flop

module gate(clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk)begin
if(reset)
    q <= 0;
else
    q <= d;
end
                
endmodule