Assign Statement In Verilog
assign keyword is used to assign ouput port or wire some digital logic. This keyword is the part of dataflow modeling in Verilog. In this post, we will see how to use this keyword in your Verilog code
- You can use assign statement inside of module.
- You can use assign statement to output port and any wire declared inside the module
Examples of assign statement
AND gate
module gate(a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
In above example, y is output port and we are assigning this output port to a and b. It will create a and gate where a and b are inputs and y is output
NAND gate
module gate(a,b,y);
input a,b;
output y;
wire w;
assign w = a & b;
assign y = ~w;
endmodule
In above example, we've descrived a NAND gate. We can use one statemetn but for better understanding we've use two statement to illustrate how we can use assign statement to both wire and output port. wire w is assign with a AND b, and output y is assigned not of wire w. This creates a NAND gate in verilog HDL.
Full adder
module fulladder(a,b,cin,sum,carry);
input a,b;
output y;
wire w;
assign sum = a ^ b ^ cin;
assign carry = (a&b) | (b&cin) | (cin & a);
endmodule
In above example, we have described a full-adder using assign statement. Note that we can write complete boolean equation using assign statement
Operators
We can also use Verilog operators using assign statement. Below is the example of full-adder using assign statement and Verilog operator
module fulladder(a,b,cin,sum,carry);
input a,b;
output y;
assign {carry,sum} = a + b + cin;
endmodule
In above example, we are using + operator, which addition operator in Verilog. We are assigning output sum and carry with addition of a, b and cin.
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