Behavioral Modeling In Verilog
Behavioral Modeling is the highest level of abstraction in Verilog.
Keywords Required
- always @(*)
- reg
- wire
- if
- else
Behavioral Modeling has lots of more keywords but we are not discussing all of them here better understanding because in this part, we are only describing a combinational circuit.
Very Important Rule
Inside the always block, if we are assigning something it must be reg type
Describe a hardware using these keyowrds
Let us describe a 4X1 MUX using data flow modeling. Write the boolean expression and make a logic circuit diagram.
Boolean Expression
$$Y = \bar S I_0 + S I_1$$
Algorithm
2X1 MUX selects the inputs based on select line. If select line is 0, I0 is selected else I1 is selected. Similarlly, we can describe MUX using behavioural modeling by writing this algorithm.
First make a module and list input output ports and make procedural block (always block)
Write algorithn inside the always block. Thats it 😀
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