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Ishaan
Posted on 16 Aug 2023

Blocking and Non-blocking Assignment in Verilog

When working with behavioural modeling in Verilog, there are two types of assigment which is known as blocking and non blocking assigment and both of them there is a operator, '=' operator for blocking assignment and '<=' operator for non blocking assigment. At short, blocking assignment executes one by one sequentially and non-blocking assignemnt executes parallelly at the same time. Let's see what is the difference between these two in detail , and before going in detail of this, let's us clear some important points about behavioural modeling.

  • Assignment is only done in procedural block(always ot initial block)
  • Both combintational and sequential circuit can be described.
  • Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

reg [2:0] shift;

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

module shift_reg(
    input clk,d,
    output reg [2:0] shift
    );

always @(posedge clk)begin
    shift[0] <= d;
    shift[1] <= shift[0];
    shift[2] <= shift[1];
end

endmodule

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

module shift_reg(
    input clk,d,
    output reg [2:0] shift
    );

always @(posedge clk)begin
    shift[0] = d;
    shift[1] = shift[0];
    shift[2] = shift[1];
end

endmodule
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