D Flip-flop in Verilog
D flip-flop is the most important flip-flop in digitial circuit. In this tutorial, we'll descrive D flip-fop in Verilog HDL without reset, with synchronous and asynchronous reset.
D flip-flop is also known as delay type flip-flop because output of d flip-flop is 1 clock pulse delay of the input appled to the d flip-flop . The truth table of positive edge triggered D flip-flop is given below. When there is negative edge trigger clock, it stores the previous input applied to the flip-flop. In positive edge trigger of clock, input of the d flip-flop is stored.
D flip-flop Truth Table
Clock Edge |
D |
Q |
Description |
|
$$\downarrow$$ |
X |
Q |
No Change (Store previous input) |
|
$$\uparrow$$ |
1 |
1 |
Set Q to 1 |
|
$$\uparrow$$ |
0 |
0 |
Reset Q to 0 |
Verilog Code of D flip-flop
D flip-flop without reset
module dff(clk,d,q);
input clk,d;
output reg q;
always @ (posedge clk)begin
q <= d;
end
endmodule
D flip-flop with synchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk)begin
if(reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop with asynchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk or negedge reset)begin
if(~reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop without reset
module dff(clk,d,q);
input clk,d;
output reg q;
always @ (posedge clk)begin
q <= d;
end
endmodule
D flip-flop with synchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk)begin
if(reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop with asynchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk or negedge reset)begin
if(~reset)
q <= 0;
else
q <= d;
end
endmodule
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