D Flip-flop in Verilog
D flip-flop is the most important flip-flop in digitial circuit. In this tutorial, we'll descrive D flip-fop in Verilog HDL without reset, with synchronous and asynchronous reset.
D flip-flop is also known as delay type flip-flop because output of d flip-flop is 1 clock pulse delay of the input appled to the d flip-flop . The truth table of positive edge triggered D flip-flop is given below. When there is negative edge trigger clock, it stores the previous input applied to the flip-flop. In positive edge trigger of clock, input of the d flip-flop is stored.
D flip-flop Truth Table
Clock Edge |
D |
Q |
Description |
|
$$\downarrow$$ |
X |
Q |
No Change (Store previous input) |
|
$$\uparrow$$ |
1 |
1 |
Set Q to 1 |
|
$$\uparrow$$ |
0 |
0 |
Reset Q to 0 |
Verilog Code of D flip-flop
D flip-flop without reset
module dff(clk,d,q);
input clk,d;
output reg q;
always @ (posedge clk)begin
q <= d;
end
endmodule
D flip-flop with synchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk)begin
if(reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop with asynchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk or negedge reset)begin
if(~reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop without reset
module dff(clk,d,q);
input clk,d;
output reg q;
always @ (posedge clk)begin
q <= d;
end
endmodule
D flip-flop with synchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk)begin
if(reset)
q <= 0;
else
q <= d;
end
endmodule
D flip-flop with asynchronous reset
module dff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk or negedge reset)begin
if(~reset)
q <= 0;
else
q <= d;
end
endmodule
Click like if you found this useful
Add Comment
This policy contains information about your privacy. By posting, you are declaring that you understand this policy:
- Your name, rating, website address, town, country, state and comment will be publicly displayed if entered.
- Aside from the data entered into these form fields, other stored data about your comment will include:
- Your IP address (not displayed)
- The time/date of your submission (displayed)
- Your email address will not be shared. It is collected for only two reasons:
- Administrative purposes, should a need to contact you arise.
- To inform you of new comments, should you subscribe to receive notifications.
- A cookie may be set on your computer. This is used to remember your inputs. It will expire by itself.
This policy is subject to change at any time and without notice.
These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:
- Although the administrator will attempt to moderate comments, it is impossible for every comment to have been moderated at any given time.
- You acknowledge that all comments express the views and opinions of the original author and not those of the administrator.
- You agree not to post any material which is knowingly false, obscene, hateful, threatening, harassing or invasive of a person's privacy.
- The administrator has the right to edit, move or remove any comment for any reason and without notice.
Failure to comply with these rules may result in being banned from submitting further comments.
These terms and conditions are subject to change at any time and without notice.
Comments (1)
very informative!