Data Flow Modeling is the 3rd level of abstraction in Verilog.
In above keywords assign is known as continious assignment keyword. and using wire keyword we can declare internal connections.
Let us describe a 4X1 MUX using data flow modeling. Write the boolean expression and make a logic circuit diagram.
$$Y = \bar S_1 \bar S_0 I_0 + \bar S_1 S_0 I_1 + S_1 \bar S_0 I_2 + S_1 S_0 I3$$
First, create a module and define input output ports. Declare internal connection using wire keyword.
By usign assign statement write the boolean expression in a single line. Thats it 😀
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