initial block is much similar to always block but initial block only executes once in entire program and it is non synthesizable Veilog.
1. If there is multi-line statement in initial block, use begin and end statement and wire code inside begin and end
2. assigning inside initial block must be reg type
Initial block is used to initialise the value of register, or flip-flop in testbench. You can initialise clock register so that you can generate clock. you can generate testcases for test module inside initial block
module testb; reg clk; initial begin clk = 0; //initialise clock to 0 end always #10 clk = ~ clk; //generates clock endmodule
module testb; reg a,b; wire y; andgate uut(a,b,y); initial begin a = 0; b = 0; //test cases #10 a = 0; b = 1; #10 a = 1; b = 0; #10 a = 1; b = 1; #10 $finish(); end endmodule
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