JK Flip-flop in Verilog

In this tutorial, we'll decribe JK flip flip withour reset, with synchronous reset and asynchronous reset.

JK flip-flop without reset

module jkff(clk,j,k,q);
input clk,j,k;
output reg q;

always @ (posedge clk)begin
        case({j,k})
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= ~q;
            default:
                q <= q;
        endcase
end
                
endmodule

JK Flip-flop with synchronous reset

module jkff(clk,j,k,q);
input clk,reset,j,k;
output reg q;

always @ (posedge clk)begin
    if(reset)
        q <= 0;
    else begin
        case({j,k})
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= ~q;
            default:
                q <= q;
        endcase
    end
end
                
endmodule

JK flip-flop with asynchronous reset

module jkff(clk,j,k,reset,q);
input clk,reset,j,k;
output reg q;

always @ (posedge clk or negedge reset)begin
    if(~reset)
        q <= 0;
    else begin
        case({j,k}) 
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= ~q;
            default:
                q <= q;
        endcase
    end
end
                
endmodule