Logic gates are the building block of digital circuit and system. We can make any digital circuit using logic gates. The are three basic logic gates AND, OR and NOT gate, two universal gate NAND and NOR and two other logic gates Ex-OR and EX-NOR. In this post, how to write Verilog code for logic gates is discussed.

There are three Verilog codes for each logic gate, you can use any one code.

NOT gate has one input and one output and both are complement of each other. If input is 1 output is 0 and vice versa. The truth table of NOT gate is given below and we can write bolean expression of NOT gate as $$y = \overline a \text{ or } y = a'$$ $$\text{Where a is input and y is output}$$

## Input a |
## Output y |

0 |
1 |

1 |
0 |

```
//NOT gate using Structural modeling
module not_gate_s(a,y);
input a;
output y;
not(y,a);
endmodule
```

```
//NOT gate using data flow modeling
module not_gate_d(a,y);
input a;
output y;
assign y = ~a;
endmodule
```

```
//NOT gate using behavioural modeling
module not_gate_b(a,y);
input a;
output reg y;
always @ (a)
y = ~a;
endmodule
```

```
module not_gate_tb;
reg a;
wire y;
not_gate_s uut(a,y);
initial begin
a = 0;
#10
b = 1;
#10
$finish();
end
endmodule
```

AND gate has many inputs (it can be two or more than two inputs) and one output. Output of the AND gate is 1 if and only if all of the inputs are 1. The truth table of 2-input AND gate is given below and we can write boolean expression for AND gate as follows $$y = ab \text{ or } y = a.b$$

## Input a |
## Input b |
## Output y |

0 |
0 |
0 |

0 |
1 |
0 |

1 |
0 |
0 |

1 |
1 |
1 |

```
//AND gate using Structural modeling
module and_gate_s(a,b,y);
input a,b;
output y;
and(y,a,b);
endmodule
```

```
//AND gate using data flow modeling
module and_gate_d(a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
```

```
//AND gate using behavioural modeling
module AND_gate_b(a,b,y);
input a,b;
output y;
always @ (a,b)
y = a & b;
endmodule
```

```
module and_gate_tb;
reg a,b;
wire y;
and_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

OR gate has many inputs (it can be two or more than two inputs) and one output. Output of the OR gate is 1 if one or more than one inputs are 1. The truth table of 2-input OR gate is given below and we can write boolean expression for OR gate as follows $$y = a + b$$

## Input a |
## Input b |
## Output y |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
1 |

```
//OR gate using Structural modeling
module or_gate_s(a,b,y);
input a,b;
output y;
or(y,a,b);
endmodule
```

```
//OR gate using data flow modeling
module or_gate_d(a,b,y);
input a,b;
output y;
assign y = a | b;
endmodule
```

```
//Not gate using behavioural modeling
module or_gate_b(a,b,y);
input a;
output y;
always @ (a,b)
y = a | b;
endmodule
```

```
module or_gate_tb;
reg a,b;
wire y;
or_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

NAND gate has many inputs (it can be two or more than two inputs) and one output. It is AND gate followed by NOT gate and output of the NAND gate is 0 if all inputs are 1 else it is 1. The truth table of 2-input NAND gate is given below and we can write boolean expression for OR gate as follows $$y = \overline{ab} \text{ or } \overline{a.b}$$

## Input a |
## Input b |
## Output y |

0 |
0 |
1 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

```
//NAND gate using Structural modeling
module nand_gate_s(a,b,y);
input a,b;
output y;
nand(y,a,b);
endmodule
```

```
//NAND gate using data flow modeling
module nand_gate_d(a,b,y);
input a,b;
output y;
assign y = ~(a & b);
endmodule
```

```
//NAND gate using behavioural modeling
module nand_gate_b(a,b,y);
input a;
output reg y;
always @ (a,b)
y = ~(a & b);
endmodule
```

```
module nand_gate_tb;
reg a,b;
wire y;
nand_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

NOR gate has many inputs (it can be two or more than two inputs) and one output. It is NOR gate followed by NOT gate and output of the NOR gate is 1 if all inputs are 0 else it is 1. The truth table of 2-input NAND gate is given below and we can write boolean expression for OR gate as follows $$y = \overline{a+b}$$

## Input a |
## Input b |
## Output y |

0 |
0 |
1 |

0 |
1 |
0 |

1 |
0 |
0 |

1 |
1 |
0 |

```
//NOR gate using Structural modeling
module nor_gate_s(a,b,y);
input a,b;
output y;
nor(y,a,b);
endmodule
```

```
//NOR gate using data flow modeling
module nor_gate_d(a,b,y);
input a,b;
output y;
assign y = ~(a | b);
endmodule
```

```
//NOR gate using behavioural modeling
module nor_gate_b(a,b,y);
input a;
output reg y;
always @ (a,b)
y = ~(a | b);
endmodule
```

```
module nor_gate_tb;
reg a,b;
wire y;
nor_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

EX-OR gate has many inputs (it can be two or more than two inputs) and one output. The output of EX-OR gate is 1 if odd number of inputs are 1 else it is 0. The truth table of 2-input EX-OR gate is given below and we can write boolean expression for OR gate as follows $$y = a\oplus b$$

## Input a |
## Input b |
## Output y |

0 |
0 |
0 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

```
//EX-OR gate using Structural modeling
module xor_gate_s(a,b,y);
input a,b;
output y;
xor(y,a,b);
endmodule
```

```
//EX-OR gate using data flow modeling
module xor_gate_d(a,b,y);
input a,b;
output y;
assign y = a ^ b;
endmodule
```

```
//EX-OR gate using behavioural modeling
module xor_gate_b(a,b,y);
input a;
output reg y;
always @ (a,b)
y = a ^ b;
endmodule
```

```
module xor_gate_tb;
reg a,b;
wire y;
xor_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

EX-NOR gate has many inputs (it can be two or more than two inputs) and one output. The output of EX-NOR gate is 1 if even number of inputs are 1 else it is 0. The truth table of 2-input EX-NOR gate is given below and we can write boolean expression for OR gate as follows $$y = \overline{a\oplus b}$$

## Input a |
## Input b |
## Output y |

0 |
0 |
1 |

0 |
1 |
0 |

1 |
0 |
0 |

1 |
1 |
1 |

```
//EX-NOR gate using Structural modeling
module xnor_gate_s(a,b,y);
input a,b;
output y;
xnor(y,a,b);
endmodule
```

```
//EX-NOR gate using data flow modeling
module xnor_gate_d(a,b,y);
input a,b;
output y;
assign y = ~(a ^ b);
endmodule
```

```
//EX-NOR gate using behavioural modeling
module xor_gate_b(a,b,y);
input a;
output reg y;
always @ (a,b)
y = ~(a ^ b);
endmodule
```

```
module xnor_gate_tb;
reg a,b;
wire y;
xnor_gate_s uut(a,b,y);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule
```

Privacy Policy

This policy contains information about your privacy. By posting, you are declaring that you understand this policy:

- Your name, rating, website address, town, country, state and comment will be publicly displayed if entered.
- Aside from the data entered into these form fields, other stored data about your comment will include:
- Your IP address (not displayed)
- The time/date of your submission (displayed)

- Your email address will not be shared. It is collected for only two reasons:
- Administrative purposes, should a need to contact you arise.
- To inform you of new comments, should you subscribe to receive notifications.

- A cookie may be set on your computer. This is used to remember your inputs. It will expire by itself.

This policy is subject to change at any time and without notice.

Terms and Conditions

These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:

- Although the administrator will attempt to moderate comments, it is impossible for every comment to have been moderated at any given time.
- You acknowledge that all comments express the views and opinions of the original author and not those of the administrator.
- You agree not to post any material which is knowingly false, obscene, hateful, threatening, harassing or invasive of a person's privacy.
- The administrator has the right to edit, move or remove any comment for any reason and without notice.

Failure to comply with these rules may result in being banned from submitting further comments.

These terms and conditions are subject to change at any time and without notice.

{"commentics_url":"\/\/circuitfever.com\/comments\/","page_id":187,"enabled_country":false,"country_id":0,"enabled_state":false,"state_id":0,"enabled_upload":false,"maximum_upload_amount":3,"maximum_upload_size":5,"maximum_upload_total":5,"captcha":false,"captcha_url":"https:\/\/circuitfever.com\/comments\/frontend\/index.php?route=main\/form\/captcha&page_id=187","cmtx_wait_for_comment":"cmtx_wait_for_comment","lang_error_file_num":"A maximum of %d files are allowed to be uploaded","lang_error_file_size":"Please upload files no bigger than %.1f MB in size","lang_error_file_total":"The total size of all files must be less than %.1f MB","lang_error_file_type":"Only image file types are allowed to be uploaded","lang_text_loading":"Loading ..","lang_placeholder_country":"Country","lang_placeholder_state":"State","lang_text_country_first":"Please select a country first","lang_button_submit":"Add Comment","lang_button_preview":"Preview","lang_button_remove":"Remove","lang_button_processing":"Please Wait.."}

{"commentics_url":"\/\/circuitfever.com\/comments\/","auto_detect":false}

## Comments (5)

there are some errors in your tutorial:

//Not gate using behavioural modeling replace Not with Or

module or_gate_b(a,b,y);

input a; // you forgot to put b here, too

output y;

always @ (a,b)

y = a | b;

endmodule

Thanks for your notice

Amazing 👏

Send bit addition logic,base logic,pg(progate and generate), logic sum logic codes for gate level and behaviour test bench

Very good

very useful

Great job

Keep it up.