Modeling in Verilog

We can model a hardware in different level of abstraction known as structural, data flow and behavioral. If you know logic diagram of the hardware, you can use structural modeling.

Structural Modeling

Structural modeling is also known as gate level modeling. The hardware is described only using logic gates.

1. not(out,in);
2. and(out,in1,in2)
3. or(out,in1,in2)
4. nand(out,in1,in2)
5. nor(out,in1,in2)
6. xor(out,in1,in2)
7. xnor(out,in1,in2)

module and_gate_structural  (
    input a,b,
    output y
);
and(y,a,b);
endmodule

Data Flow Modeling

In data flow modeling, we describe how data is flowing from input and ouput. We use assign keyword in data flow modeling. The description of AND gate using data flow modeling is given below.

module and_gate_dataflow (
    input a,b,
    output y
);
assign y = a & b;
endmodule

Behavioural Modeling

This is the highest level of abstraction in Verilog modeling in which we describe hardware like an algorithm or any algorithm can be described using behavioral modeling. Hardware description of and gate is given below. For AND gate, output is 1 only when both inputs are 1. Few things to take care while hardware describing using behavioral.

1. Hardware is described inside always block
2. output that we are assigning something must be reg (Register) type.

module and_gate_behavioural (
  input a,b,
  output reg y
);

always @(*) begin
    if(a == 1 & b == 1)
        y = 1;
    else
        y = 0;
end
endmodule