Like other programming languages, Verilog has operators and we can use these operators to describe a hardware. Each operator is denoted by a symbol similar to the operators in other programming languages.

Here are the list of operators in Verilog.

## Symbol |
## Operation |
## Description |

+ |
Addition |
Performs Addition Operation of Two Operands |

- |
Subtraction |
Performs subtraction operation of two operands |

* |
Multiplication |
Performs Multiplication operation of two operands |

/ |
Division |
Performs division operation of two operands |

% |
Modulus |
Performs Modulus of Two Operands |

## Symbol |
## Operation |
## Description |

! |
NOT |
Performs logical not operation |

|| |
OR |
Performs logical OR operation |

&& |
AND |
Performs logical AND operation |

## Symbol |
## Operation |
## Description |

~ |
NOT |
Performs bitwise NOT operation of a operand |

| |
OR |
Performs bitwise OR operation of two operands |

& |
AND |
Performs bitwise AND operation of two operands |

^ |
Ex-Or |
Performs bitwise ex-or operation of two operands |

## Symbol |
## Operation |
## Description |

> |
Greater Than |
True if left operand is greater than right operand |

< |
Less Than |
True if left operand is less than right operand |

>= |
Greater than or equal to |
True if left operand is greater than or equal to right operand |

<= |
Less than or equal to |
True if left operand is less than or equal to right operand |

## Symbol |
## Operation |
## Description |

== |
Equal to |
True if left operand is equal to right operand |

!= |
Not equal to |
True if left operand is not equal to right operand |

## Symbol |
## Operation |
## Description |

<< |
Left Shift |
Performs left shift operation |

>> |
Right Shift |
Performs right shift operation |

<<< |
Left Shift |
Performs arithmetic left shit operation |

>>> |
Right Shift |
Performs arithmetic right shift operation |

## Symbol |
## Operation |
## Description |

~ |
NOT |
Performs reduction using NOT logic |

| |
OR |
Performs reduction using OR logic |

& |
AND |
Performs reduction using AND logic |

^ |
Ex-Or |
Performs Multiplication operation of two operands |

Curly braces is the concatination operator in Verilog we can use this to concatinate inputs and outputs. Here is an example

```
module gate(a,b,cin,sum,carry);
input a,b;
output sum,carry;
assign {carry,sum} = a + b + cin; //Concatination operator used
endmodule
```

We can replicate any inpu and output using same curly braces. Here is an example

```
module repli(a,b,y);
input a,b;
output [2:0]y;
wire x;
assign x = a & b;
assign y= {3{x}}; //replicating x three times
endmodule
```

Question mark operator is the conditional operator. and it is used as follows

**assign y = condition?(if_true_output):(if_false_output);**

We can describe 2X1 MUX using conditional operation as given below

```
module gate(a,b,s,y);
input a,b,s;
output y;
assign y = s?a:b; //conditional operator used
//If s is 1, a is selected else b is selected, which is 2X1 MUX
endmodule
```

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