reg and wire Keywords in Verilog

wire and reg is the most used keywords in verilog. Whether you are writing Verilog code or testbench, these keywords are widely used. In this post, we will see how and where to use these two keywords.

Verilog Code

wire

When we descrive a hardware in Verilog HDL, we describe a piece of hardware inside a module. While declaring a Verilog module, we list input output ports. If there is connections inside of the module, we can use wire to make connection.

module gate1(a,b,y);
input a,b;
output y;

wire w;

assign w = a & b;
assign y = ~w;

endmodule

In above example, there are two logic gates, AND gate and NOT gate. We are declaring a wire w and makeing connection between AND gate output and input of NOT gate. We can declare as many wire we want to make internal connection.

reg

reg keyword is used to decalare a register in a verilog code. reg keyword is only used in behavioral modeling because in behavioral meloding, we use procedural block (always block) and for assigning inside procedural block, the output or internal connection must be reg type.

Procedural block

module gate2(a,b,y);
input a,b;
output reg y;

always @ (*) begin
    y = a & b;
end

endmodule

In above example, we are describing a AND gate using behavioral modeling and we are declaring output as a reg type.

Sequential Circuit

If we are describing sequential circuit, we use reg to declare a register.

module dff(clk,reset,d,q);
input clk,d,reset;
output reg q;

always @ (posedge clk) begin
    if(reset)
        q <= 0;
    else
        q <= d;
end

endmodule

in above example, we are declaring a register q using reg keyword. Inside of the procedural block we are describing a D Flip-Folp. We can descrive any sequential circuit using procedual block but if we need any register, it should be delcalre using reg keyword.

testbench

In a testbench, wire is used to make connection to output ports of the test module and reg is used to generate test cases for the test module.

module gate_tb;
reg a,b;
wire y;

gate1 uut(a,b,y);

initial begin
a = 0; b = 0;
#10
a = 0; b = 1;
#10
a = 1; b = 0;
#10 
a = 1; b = 1;
#10
$finish();
end

endmodule

Above example is a testbench for NAND gate which is described above. We are declaring reg for input so that we can give test input to the test module and declaring wire for output of test module so that we can observe the output of the testing module.