SR Flip-flop in Verilog

SR flip-flop or SET RESET flip-flop stores 1-bit data. We can store 1 or 0 to the flip-flop by applying input accordingly. If S is 1 and R is 0, it stores 1. If S is 0 and R is 1 it store 0. In this tutorial we'll describe SR flip-flop in Verilog HDL.

The positive edge triggerd SR flip-flop truth table is given below

Verilog Code of SR flip-flop

SR flip-flop without reset

module srff(clk,s,r,q);
input clk,s,r;
output reg q;

always @ (posedge clk)begin
        case({s,r})
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= 1'bx;
            default:
                q <= q;
        endcase
end
                
endmodule

SR flip-flop with synchronous reset

module srff(clk,reset,s,r,q);
input clk,reset,s,r;
output reg q;

always @ (posedge clk)begin
    if(reset)
        q <= 0;
    else begin
        case({s,r})
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= 1'bx;
            default:
                q <= q;
        endcase
    end
end
                
endmodule

SR flip-flop with asynchronous reset

module srff(clk,reset,s,r,q);
input clk,reset,s,r;
output reg q;

always @ (posedge clk or negedge reset)begin
    if(~reset)
        q <= 0;
    else begin
        case({s,r})
            2'b00:
                q <= q;
            2'b01:
                q <= 0;
            2'b10:
                q <= 1;
            2'b11:
                q <= 1'bx;
            default:
                q <= q;
        endcase
    end
end
                
endmodule