Circuit Fever Author - Rohit
Posted on 26 July 2023

How to Store An Image on FPGA (BRAM)?

If you are working on an Image processing reated applications on FPGA, you must have faced a problem of how to store an image on FPGA? Maybe a random numbers can be used as an image? or is there any other way to getting things done?. An image has lots of pixel and each pixel has some value and if somehow you can extract the pixel values then we can use the pixel values in our FPGA project. An image has lots of pixels how we can manage those? If we want to store an image on FPGA, first we have to extract pixel values. This can be done by scripted languages like Python. If somehow we can transfer these pixel values to Block Random Access Memory of FPGA, we can then do whatever image processing we want to perform on FPGA.

Pixel Values Extraction

Each pixel have bit depth like 8-bit, 16-bit or something else and we can't read this directly from an image file because most of the image is compressed, it may have other information other than pixel, may have more dimentions(if an image is grayscle it may more than 2D). Ther are lots of libraries are availabe in Python, we'll use one of them.

from PIL import Image
import numpy as np

img ='./image.jpg') #Open an image from current directory
gray_img = img.convert('L') #convert image to greyscale
img_arr = np.array(gray_img) #convert image to 2d array of pixel values
d1 = img_arr.flatten() #convert to 2d to 1d array

file = open("image_pixel.coe","w")  #create a new coefficient file

file.write("memory_initialization_radix=10;") #first line
file.write("memory_initialization_vector=")   #pixel values starts here
for x in range(0,len(d1)):
    file.write(" ")
file.write(";") #closing of coe file
file.close()    #close the file

Create BRAM and load file

The size of the image is 256x256 pixels and each pixel requires 8 bit width. So we require BRAM of depth 65536 and width 8.

create BRAM for loading image

After creation of BRAM with required width and depth, load the coe file generated form the above python code which contains the all pixel information. You can click on Other options of the BRAM wizard, click on browse button and load the coe file.

load image file to BRAM

Verilog Code and Testbench

module image_test;
reg clk = 0;
reg [15:0]address = 0;
wire [7:0]data_out,data_in;

wire read_write = 0;
integer i;
blk_mem_gen_0 uut(.clka(clk),.addra(address),.dina(data_in),.douta(data_out),.wea(read_write));

initial begin
for(i = 0; i < 65536; i= i+1)begin
    address = i;

always #10 clk = ~clk;

simulation output

Learn FPGA Implementation

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