After switch level modeling, Structural modeling is the lowest level of abstraction in verilog. It is also called gate level modeling because we only describe a hardware in logic gates and their inteconnections.
In above keywords of logic gates, inside the parentheses we are required to list input and output connections. In all of the above logic gate keywords, first list will be output and rest will be inputs. For example and(y,a,b); instantiate a AND gate with output y and inputs a,b.
Using wire keyword, you can make internal connections between the logic gates. To make internal connections, we are required to declare the internal wire name. For exmaple wire x; will declare a wire which has name x.
Let us describe a 2X1 MUX using structural modeling. Write the boolean expression and make a logic circuit diagram.
$$Y = \bar S I_0 + S I_1$$
First, create a module and define input output ports. Make logic gates by instantiating respective logic gate keyword. There is two AND gate, one OR gate and one NOT gate.
Declare internal connection using wire keyword.
Now make connection between logic gates and input output ports.
After making connections, synthesize the design and you'll see the output diagram of your described hardware.
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