Useful System Tasks and Functions in Verilog
System tasks and functions are useful in both RTL design and RTL verification. These make us getting things done easier. Verilog has various system tasks and function but, we will cover most used or useful of them.
Display Tasks
These tasks are useful when printing the values of various variables or design under test module. Display task is much similar to printf function of C language. The syntax is given below:
$display("%d", a);
Above line displays the current value of the register or wire a.
Finish Tasks
This tasks terminate the simulation of a Verilog testbench whenever it reaches to this line.
$finish();
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