System tasks and functions are useful in both RTL design and RTL verification. These make us getting things done easier. Verilog has various system tasks and function but, we will cover most used or useful of them.
These tasks are useful when printing the values of various variables or design under test module. Display task is much similar to printf function of C language. The syntax is given below:
$display("%d", a);
Above line displays the current value of the register or wire a.
This tasks terminate the simulation of a Verilog testbench whenever it reaches to this line.
$finish();
Click like if you found this useful
This policy contains information about your privacy. By posting, you are declaring that you understand this policy:
This policy is subject to change at any time and without notice.
These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:
Failure to comply with these rules may result in being banned from submitting further comments.
These terms and conditions are subject to change at any time and without notice.
Comments