Kamal Raj
Posted on 04 Mar 2023
T Flip-flop in Verilog
In this tutorial, we'll decribe T flip flip withour reset, with synchronous reset and asynchronous reset.
T flip-flop Truth Table
Clock Edge |
T |
Q |
Description |
|
$$\downarrow$$ |
X |
Q |
No Change (Store previous input) |
|
$$\uparrow$$ |
0 |
Q |
Previous State |
|
$$\uparrow$$ |
1 |
$$\overline Q$$ |
Toogle |
T flip-flop without reset
module tff(clk,t,q);
input clk,t;
output reg q;
always @ (posedge clk)begin
if(t == 0)
q <= q;
else
q = ~q;
end
endmodule
D flip-flop with synchronous reset
module tff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk)begin
if(reset)
q <= 0;
else begin
if(t == 0)
q <= q;
else
q = ~q;
end
end
endmodule
T flip-flop with asynchronous reset
module tff(clk,reset,d,q);
input clk,reset,d;
output reg q;
always @ (posedge clk or negedge reset)begin
if(~reset)
q <= 0;
else begin
if(t == 0)
q <= q;
else
q = ~q;
end
end
endmodule
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