T Flip-flop in Verilog

In this tutorial, we'll describe a T flip flip without reset, with synchronous reset and asynchronous reset.

T flip-flop without reset

module tff(clk,t,q);
input clk,t;
output reg q;

always @ (posedge clk)begin
    if(t == 0)
        q <= q;
    else 
        q = ~q;
end
                
endmodule

T flip-flop with synchronous reset

module tff(clk,reset,d,q);
input clk,reset,t;
output reg q;

always @ (posedge clk)begin
    if(reset)
        q <= 0;
    else begin
    if(t == 0)
        q <= q;
    else 
        q = ~q;
    end
end
                
endmodule

T flip-flop with asynchronous reset

module tff(clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk or negedge reset)begin
    if(~reset)
        q <= 0;
    else begin
    if(t == 0)
        q <= q;
    else 
        q = ~q;
    end
end
                
endmodule