UART Communication in FPGA
A UART is a simple and lightweight serial communication protocol found in most embedded systems. Since the FPGA or any hardware chip has limited input-output ports, communication capability is required to transfer data to the FPGA. In some scenarios, the data needs to be transferred between a PC and the FPGA. Most FPGA boards have a USB-UART bridge, which allows the FPGA to communicate using the UART protocol.
The UART Protocol
The Universal Asynchronous Receiver Transmitter, or UART, is a refreshingly simple serial communication protocol. It operates with just one wire for simplex communication or two wires for half-duplex or duplex communication. These wires are known as the TX (transmitter pin) and RX (receiver pin). For successful communication, all you need to do is connect the sender's TX pin to the receiver's RX pin, and vice versa. It's that straightforward.
USB-UART Bridge
Most USB-UART bridges have FTDI-integrated circuits. They usually require no configuration; you can plug in an FPGA and a PC with a USB and exchange data. In some FPGA boards, like the board with the Zynq processing system (PS), the UART is connected to the PS, and you can't directly use it from the programming logic (PL). In this case, you can connect an external USB-UART bridge to the PMOD and exchange data between the FPGA and PC.
The UART Hardware implementation
If you're considering implementing UART in PL, you're in luck. The Verilog implementation is readily available in the GitHub repository. Simply click on the link below to access the Verilog code. This implementation includes both transmitter and receiver code, giving you the power to control the communication process.
Start Communication
The implementation consists of a test top module and an echo UART. Whatever you send to the FPGA from the PC will be sent back to the PC. Create a constraints file, make proper connections to the master clock, TX, RX, and done signals, generate a bitstream, and program the FPGA.
Install Python on your PC. Then, install the pyserial package. Run the testuart.py script. If UART communication works, the script will display the same data you sent to the FPGA. If not, you have to debug it.
Debug Mode On
If you are unable to communicate with the FPGA, first make sure the board has a USB-UART bridge that can be connected to the PL. Identify the correct TX and RX pins and connect them correctly. Identify the correct FPGA board master clock frequency and enter it in the clock generator module.
If it is still not working, create a Verilog module with only TX and RX pins, assign TX to the RX, update the constraints file for it, generate the bitstream, and program the FPGA. Run the testuart.py Python script and see if it is working. If not, reverse the TX and RX pin connections in the constraint file and implement it in the FPGA (sometimes TX and RX pins are displayed in reverse in the user manual or master constraints file). Rerun the test script.
