Vector in Verilog
Scalar or vecor in Verilog is basically number of bits we are perfoming operation. If we are performing operation into a single bit then it is scalar and if it is n-bit, then it is vector. In this post, we'll see how we can use vector in Verilog HDL
Scalar example
module gate(a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
In above example, inputs and output is scaler and it is of 1-bit in size.
Vector Example
module gate(a,b,y);
input [1:0]a,b;
output [1:0]y;
assign y = a & b;
endmodule
In above example, we are declaring vector or n-bit input output ports where [1:0] is [msb:lsb]. Msb is 1 and lsb is 0, it means we have declared 2-bit input and output.
This creates a 2-bit AND gate or two AND gate.
We can also access single bit form n-bit declaration. For example
module gate(a,b,y);
input a,b;
output [1:0]y;
assign y[0] = a & b;
assign y[1] = a | b;
endmodule
Above example create 2 gates but the difference is it will create one AND gate and one OR gate. We can use indexing for accessing a single bit as coded in above example.
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