Compiler Directive in Verilog

Compiler directive are the instructions for the compiler which tells the compiler how to process the Verilog source code before synthesis for compiling the source code. It can be very useful when dealing with a large codebase or designer wish to make the source code more clear and elegant to human read. It is also analogous to compiler directive in C/C++ code. The compiler directive in Verilog starts with a backtick (`) symbol. If you found this in any Verilog souce code, you know it's a compiler directive. In this post, we will learn about some very useful compiler directive which you can use in your Verilog code.

include

As name suggest, include compiler directive is use to tell the compiler to include everything from a other Verilog file. If you have multiple Verilog file and you don't want to just copy past, you can use this compiler directive.

timescale

This compiler directive is used to tell the compiler about the timing information about your design.

define and undef

This compiler directive is used to declare or undeclare a variable to the compiler.

ifdef elif and else

It is like regular if-else statement but it is to tell the compiler which part of the code to use in the design or which part of the code to exclude from the design.