How to Write Testbench In Verilog

Testbench are very important in Verilog when you describe a hardware in Verilog. Using testbench, you can verify the functionality of your hardware whether your hardware is generating same output as expected or not.

Testbench is a module in Verilog which generates test input for your top module. It does't have any input output port. It only as has top module instantiated on it and code for generating test inputs.

Top Module

Top module is the one which you want to test. It can have multiple module instantiated inside it. Lets see an example of a full-adder designed using half-adder in Verilog.

/*
Module     : full_adder.v
Created By : circuitfever.com
Create on  : 14-02-2023
*/
module full_adder(a,b,c_in,sum,carry);
input a,b,c_in;
output sum,carry;
wire w1,w2,w3;

halfadder ha0(a,b,w1,w2);
halfadder ha1(c_in,w1,sum,w3);

assign carry = w2 | w3;

endmodule

Description of half-adder.

/*
  Module     : halfadder.v
  Created By : circuitfever.com
  Create on  : 07-11-2022
*/
module halfadder(
  input a,b,
  output sum,carry
);
xor(sum,a,b);   //sum = a exor b
and(carry,a,b); //carry = a and b
endmodule

Let's create testbench for full-adder design.

Write Testbench

First, create a test module and note that there should not be any input output ports. Because test module generate inputs for top module from inside only. So, there is no need of input output ports.

module full_adder_tb;

endmodule

Instantiate top module inside of the test module.

module full_adder_tb;

full_adder uut();

endmodule

For generating inputs for top module, declare registers and for observing output, declare wire.

module full_adder_tb;

reg a,b,c_in;
wire sum,carry;

full_adder uut();

endmodule

Make connections for input and output ports of top module. Connect registers with input port of top module and connect wire with output ports of top module.

module full_adder_tb;

reg a,b,c_in;
wire sum,carry;

full_adder uut(a,b,c_in,sum,carry);

endmodule

Create initial block for generating test cases for top module.

module full_adder_tb;

reg a,b,c_in;
wire sum,carry;

full_adder uut(a,b,c_in,sum,carry);

initial begin
//Write test cases here
end

endmodule

Generate test cases inside initial block. There are three inputs so there will be maximum 8 test cases. We can generate as many test cases we want.

/*
Module     : full_adder_tb.v
Created By : circuitfever.com
Create on  : 14-02-2023
*/
module full_adder_tb;

reg a,b,c_in;
wire sum,carry;

full_adder uut(a,b,c_in,sum,carry);

initial begin
a = 0; b = 0; c_in = 0;
#10
a = 0; b = 0; c_in = 1;
#10
a = 0; b = 1; c_in = 0;
#10
a = 0; b = 1; c_in = 1;
#10
a = 1; b = 0; c_in = 0;
#10
a = 1; b = 0; c_in = 1;
#10
a = 1; b = 1; c_in = 0;
#10
a = 1; b = 1; c_in = 1;
#10
$finish();
end

endmodule

Testbench for full-adder is ready and you can simulate this testbench and see the input output waveforms.