Verilog is a hardware description language, we can describe a hardware in a text and later we can synthesis text to generate netlist which will later generate a hardware. We can describve any digial system (hardware) in Verilog. When you start learn Verilog it is must that you should learn basics.
Each verilog file has extension of dov v (filename.v)
Like C/C++, Verilog also has single line and multi-line comment.
Module is a piece of hardware in Verilog. Each verilog syntax start with module and ends with endmodule
Each and every module in verilog has uniques name. If your design uses more than one module, then each module should have unique module name.
As any hardware has input and output ports simillarly, module also has input and output port declaration and it must be declared (Except test bench). Input port is declared using input keyword and output is declared using output keyword.
Hardware is described inside the module and endmodule. The description of the hardware can be any modeling type (structural, data flow or behavioural)
Let us describe a half adder using Verilog HDL.
Click like if you found this useful
This policy contains information about your privacy. By posting, you are declaring that you understand this policy:
This policy is subject to change at any time and without notice.
These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:
Failure to comply with these rules may result in being banned from submitting further comments.
These terms and conditions are subject to change at any time and without notice.
Comments