# Basics of Verilog

Verilog is a hardware description language, we can describe a hardware in a text and later we can synthesis text to generate netlist which will later generate a hardware. We can describve any digial system (hardware) in Verilog. When you start learn Verilog it is must that you should learn basics.

## File Extension

Each verilog file has extension of dov v (filename.v)

Like C/C++, Verilog also has single line and multi-line comment.

1. //This is single line comment
2. /*
This is multi-line
comment
*/

## Module

Module is a piece of hardware in Verilog. Each verilog syntax start with module and ends with endmodule

### Module name

Each and every module in verilog has uniques name. If your design uses more than one module, then each module should have unique module name.

### Port Declaration

As any hardware has input and output ports simillarly, module also has input and output port declaration and it must be declared (Except test bench). Input port is declared using input keyword and output is declared using output keyword.

### Hardware description

Hardware is described inside the module and endmodule. The description of the hardware can be any modeling type (structural, data flow or behavioural)

## Example

Let us describe a half adder using Verilog HDL.

1. Let's create a module
2. Let us choose halfadder as module name
3. Half adder has two inputs a and b and two outputs sum and carry let's declare it.
4. Boolean expression of full adder is $$sum = a \oplus b$$ $$carry = ab$$ let's describe it.

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