Getting Started With Verilog HDL

Verilog hardware description language or Verilog HDL is a standard language to describe a digital system. We can describe a hardware in a text and then we can generate netlist from the Verilog source file. We can describe any digial system (hardware) in Verilog. When you start learn Verilog, it is very important to learn basics first.

File Extension

Each verilog file has extension of dov v (filename.v)

Comments

Like C/C++, Verilog also has single line and multi-line comment.

1. //This is single line comment
2. /*
   This is multi-line
   comment
   */

Module

Module is a piece of hardware in Verilog. Each verilog syntax start with module and ends with endmodule

Module name

Each and every module in verilog has uniques name. If your design uses more than one module, then each module should have unique module name.

Port Declaration

As any hardware has input and output ports simillarly, module also has input and output port declaration and it must be declared (Except test bench). Input port is declared using input keyword and output is declared using output keyword.

Hardware description

Hardware is described inside the module and endmodule. The description of the hardware can be any modeling type (structural, data flow or behavioural)

Example

Let us describe a half adder using Verilog HDL.

1. Let's create a module
2. Let us choose halfadder as module name
3. Half adder has two inputs a and b and two outputs sum and carry let's declare it.
4. Boolean expression of full adder is $$sum = a \oplus b$$ $$carry = ab$$ let's describe it.

Now we know the very basic of the Verilog HDL and wee need to run this code or hardware description in Verilog synthesis tool. There are open source tool you can use to do synthesis or simulate the above Verilog Code. Below is the link of a tutorial in which how to install tools and simulate Verilog code is discussed.

Simulating Verilog HDL using iVerilog and GTKwave