FPGA is a very powerful technology to implement digital system in lab rapidly. We can implement any digital system in FPGA and for implementation we have to follow various steps which is discussed below. FPGA implementation requires various toolchain for synthesis, placement and routing, bitstream generation. But if you are using tools like Xilinx Vivado, you do not need to worry about installing all the toolchain because it already has all the toolchain required for FPGA development.
RTL description is stand for Register Transfer Level description is basically describing a hardware using HDL like Verilog or VHDL. For describing a hardware using HDL, you only need a text editor.
RTL Elaboration is a tool which checks your described HDL whether it has some problem like syntax error, unconnected wire, undefined port name etc and some tools will show a logic circuit diagram after RTL Elaboration.
You can check the functionality of described HDL using simulation by writing test bench. Either you can check output in console or you can see waveform.
Synthesis is conversion of HDL code to netlist. Synthesis tool takes your HDL text file and convert it to netlist and this netlist will be used by other tools for implementation.
Implementation takes netlist created by synthesis tool and do logic mapping in LUT, Flip-flop, BRAM etc. Mapping depends on the resources available on FPGA for example if your design has a memory block and if FPGA has BRAM then it will be mapped into BRAM otherwise it will be mapped to LUTs. By default mapping is done by the tool itself but you can also do manual mapping.
When implementation is done, the tool will generate another netlist which has FPGA implemented resources and their connections. PnR or Placement and Routing places the logic design in LUTs and flip-flops etc and makes connection between those. For example, if your design has a AND gate and it required only one LUT2, but your FPGA may have hundreds for LUTs. Where to place that implemented LUT and which pin to choose for making connection is PnR. By default it is done by the tool itself but you can mannually do the PnR.
After the implementation you are reauired to generate bitstream. This is the file which can be writted to the FPGA Bitstream is only generated when there is no error in entire FPGA design flow. If your design has errors, you'll not be able to generate bitstream. You have you correct errors shown in console or error log and then you can generate bitstream.
After bitstream generation is completed then you can connect FPGA to your PC and program the FPGA. A simple and practical FPGA design flow can be found Here
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